You've probably heard the term "process node leadership" being tossed around from the red camp lately; AMD has been unable to use the term until recently with the advent of the Ryzen 3000 processor, manufactured on TSMC's 7nm process node. Behind the scenes of chip manufacturing, however, there is an even bigger debate going on: what determines the name of a process node and what it means.

In a recent paper, researchers suggest that semiconductor companies should abandon loosely defined transistor gate lengths (such as 7 nm or 14 nm) as a measure of technological progress and focus instead on transistor density. This is almost the same metric that Intel has been proposing for years, but this time TSMC, Intel's biggest competitor, has tacitly agreed.

At least one TSMC researcher supports it. The paper is titled "A Density Metric for Semiconductor Technology" and is published in Proceedings of the IEEE, vol. 108, no. 4, pp. 478-482, April 2020.4 published in April (via TechPowerUp).The nine authors are from Stanford University, Massachusetts Institute of Technology (MIT), Berkeley, and TSMC. Within the team, the authors state that changes are needed to standardize advances in semiconductor lithography manufacturing technology across the industry.

This is a proposal to confront an age-old problem: you will often hear the terms 14nm, 12nm, 10nm, and 7nm. Because these are the key technologies underlying Intel, AMD, and Nvidia chips. The smaller the better.

Well, not exactly. Despite the general trend toward smaller transistor lengths, which indicates improved power efficiency and performance, it is not always that simple. Many competing technologies and companies are involved and follow their own rules for defining transistor length, so the name given to a process node is more of a marketing term than a technical term. [This label is decoupled from the actual minimum gate length, which may be several times smaller than the actual minimum gate length. [With up to 40% disparity in power and performance between nodes on a line, process node performance is an important metric in determining which chip has the best CPU for a gaming crown.

TSMC is already working on the 2nm process node and will reach that point sooner than expected. As far as semiconductors are concerned, silicon still has legs, so it is best to find a new metric for its sharpness. It is also the perfect time to finally "clean up the node name mess," as Intel once put it.

The research paper outlined in IEEExplore defines a process to measure semiconductor progress by another metric: density. It too is a holistic approach. Rather than simply measuring the length of logic transistors, it proposes to measure logic, memory, and packaging/integration technologies simultaneously. [17] [18] "Since its inception, the semiconductor industry has used physical dimensions (minimum gate length of a transistor) as a means of measuring continuous technological progress," the researchers state in their paper. This metric is largely obsolete today. As an alternative, we propose a density metric that aims to capture how advances in semiconductor device technology enable system-level benefits."

This is called the Logic, Memory, Connectivity Metric, or LMC for short, which replaces a single transistor length with three numbers consisting of DL, DM, and DC values, where DL is the density of logic transistors, DM is the main memory (today mostly off-chip DRAM) bit density, and DC is the density of connections between main memory and logic. The unit for all of these is mm2.

LMC is more advantageous for systems with lots of cores, memory, and bandwidth, such as supercomputers.

This is the problem with LMC: it is a system metric rather than a direct measurement of the lithographic process we use today. Moreover, the measure of a chip's value will vary widely from machine to machine and will be generated abstractly from the system configuration, which is dependent on components such as system memory. The first measurement, DL, would serve as a more accurate analogue of the measurements currently used throughout the industry.

A specific transistor density metric, much like DL, is one that Intel has long wanted the industry to adopt. Mark Bohr, Intel's former director of process, proposed a solution that measures the density of a 2-input NAND cell and a scan flip-flop cell and outputs a single transistor/mm2 measurement. Since this approach does not take into account SRAM cell sizes, which vary widely from chip to chip, Intel suggests including a separate measurement in parallel with the logic density

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Intel seems keen to adopt a new standard metric, as it currently tends to lead with raw transistor density. Intel reports a density of 100.76 MTr/mm2 (mega-transistors per square millimeter) for its 10nm process, while TSMC's 7nm process is a bit behind at 91.2 MTr/mm2 (via Wikichip). Intel has yet to produce a 10nm desktop processor. AMD Ryzen, on the other hand, is .......

It will take some convincing to shift the entire industry from a "proof is in the pudding" approach to universal density metrics, but both researchers and Intel agree that the density approach will prove universally more useful in measuring semiconductor progress. The three LMC metrics will also serve as indicators of the improvements that are being made as a result of the many advanced packaging technologies under development, such as 3D stacking.

So, we should expect to see LMC, or something similar, in future process nodes. As the researchers so eloquently put it, the "conundrum of harnessing the vanishing nanometer" is reaching a critical point: "The nanometer is a nanometer, and the nanometer is a nanometer, and the nanometer is a nanometer.